Conclusions And Future Scope Engineering Essay Example

in agreement with published results from different authors.Higher induced electromotive forces are observed for contact discharge ESD, with values up to 10 MHz for CSD, up to 2.5 MHz for air discharge, and in the 20 to 100 MHz range for all three types of discharge - resistive, RC shunt, and CMOS device. Contact discharge has higher induced electromotive forces compared to air discharge or CSD. The induced electromotive force in an unshielded cable increases with decreasing rise time and distance, and increasing peak amplitude and damping factor for the CSD current model. The peak value of the induced electromotive force due to IEC contact discharge ESD at 8 kilovolt is 625V for resistive discharge and 7.8 millivolt for RC shunt discharge. The peak value of the induced electromotive force due to IEC air discharge ESD at 16 kilovolt is 6.25V and 3.25 millivolt for RC shunt discharge. The peak value of the induced electromotive force at the input of a CMOS device is 14V for contact discharge and 0.6V for air discharge. It can be inferred that RC shunt discharges are preferred over resistive or CMOS device discharges as the induced electromotive forces are in the millivolt range. For shielded cable, a generic plan in Visual C++ has been implemented to calculate the induced electromotive forces for various parameters of the current waveform, length, height of the cable, and angle of incidence.This text can also be used to calculate induced electromotive forces for different cable configurations. Using MATLAB, the data imported from Visual C++ is used to calculate induced electromotive forces. The equations developed provide values for the induced electromotive forces that are in

close agreement with those published by other authors. The induced electromotive forces are analyzed for shielded cables, both braided and unbraided. The induced electromotive force and current in the central conductor are larger for a braided cable compared to a non-braided cable. This analysis determines the transient voltages at the input of the system connected to the shielded cable. This estimation can be used to develop appropriate mitigation techniques to protect the sensitive system connected to the shielded cable. Simulation calculations show that in shielded cables, the induced electromotive forces due to radiated ESD are negligible, which supports the theory that shielded cables can protect equipment from high-frequency radiated fields caused by ESD. The effect of variations in parameters such as cable length, height of the cable above the ground plane, and angle of incidence of the ESD pulse has been discussed.The peak amplitude of the sheath current in the overseas telegram decreases as the length of the cable decreases. This change is due to a smaller value of induction in shorter cables compared to longer cables. Similarly, the peak amplitude of the sheath current also decreases as the height of the cable increases.

The sheath current decreases when the angle of incidence increases, as the induced current is a function of cos(i±i). The induced electromotive force depends on both sheath current and surface transport resistance of the cable.

According to Table 3.3, for a shielded cable with a length of 1m, height of 0.1m, and angle of incidence of 30 degrees, the induced electromotive forces are 1.4-10-8V for a braided cable and 6.6-10-16V for a non-braided cable.

Mathematical analysis is utilized to simulate the response of a

Very High Frequency amplifier to Electromagnetic Discharge (ESD)-generated radiated EM fields. Using MATLAB, the effect of the radiated fields on the induced electromotive forces in a VHF amplifier at various distances from the ESD source is calculated. It is observed that a significant portion of the energy from ESD simulation currents falls within the frequency range of 200 to 400 MHz, which extends into the VHF and UHF bands. Therefore, the VHF amplifier is susceptible to ESD events within this frequency range.If the distance between the ESD generator and the pickup aerial is reduced, the amplitude of the electromotive force coupled to the amplifier input terminus increases. Additionally, the amplitude of the fields at aerial termini, unfastened circuit electromotive force at antenna input terminus, and electromotive force at the input and output of the amplifier decrease significantly as the distance from the ESD source increases. Table 4.1 shows that the induced electromotive forces at the amplifier input terminus can reach as high as 7.446 V with a rise time of approximately 1 Ns when there is a distance of 0.5 m between the ESD generator and the pickup aerial. This high electromotive force can result in malfunction of the electronic circuitry inside the amplifier. The spice circuit modeling with transient analysis confirms the experimental results for air discharge on parallel circuits. It has also been observed that the zero crossing sensor built with an opamp is more susceptible to ESD compared to the RC stage displacement oscillator built with discrete components. Experimental verification and modeling have shown that it took some time for the oscillator circuit using discrete components to return to its initial working

state after an ESD discharge due to the slow discharge of accumulated charges. In indirect discharge, it has been observed that the ESD effect depends on both distance and discharge electromotive force.In parallel circuits, higher discharge electromotive force and shorter distances result in larger transients and deformations. The opamp was damaged by a direct air discharge of 15kV at the ZCD input, but the oscillator recovered after 750µs. Similarly, a direct air discharge of 15kV at the oscillator end product affected the end product for 1.4ms. The ZCD end product remains high until the sine wave end product of the oscillator circuit recovers. The spice mold yields similar consequences for discharge at the oscillator end product. The transient looking on the ZCD end product during radiative matching may be due to differential manner, while the common manner could not be investigated. In the case of direct air discharge at the input point of the ZCD circuit, there could be two types of matching - direct capacitance matching to circuit and near field matching for the common manner. However, only the differential manner was investigated in this instance, so only differential manner transients are shown. Transients in both the differential manner and common manner were observed in direct air discharge at the oscillator end product. Unfortunately, there were no electromotive force investigations or current investigations available for high electromotive force and low rise clip within a 1ns scope with an accuracy of less than 5%. As a result, the initial rise clip and maximal amplitude of the transient could not be measured accurately through experimentation.The digital shift circuit experienced a malfunction when an Electrostatic Discharge (ESD)

event occurred 35 centimeters away from the circuit. This ESD event only affected the information stream, causing the circuit to stop working. After analyzing the post discharge, it was discovered that the Binary counter IC SN74LS393N had a functional failure, with all output pins not functioning properly. It has been proven that adding uncoupling capacitances to the supply point of each IC is important.

Experiments were conducted to study the impact of ESD on the information and clock in a digital shift circuit with uncoupling capacitances at Vcc. These experiments revealed that the effect of ESD on both the information and clock depends on the trigger location and level of matching. Discharging onto the Horizontal Yoke Plane (HCP) had different effects depending on whether the Data and Clock were High or Low. If both were High, there was an increase in information amplitude or inversion, as well as an increase in clock amplitude. The distance at which the pulse was discharged onto the HCP affected the transient's amplitude.

On the other hand, discharging onto the Vertical Yoke Plane (VCP) resulted in a loss of information and introduced a transient with a peak amplitude of over 50V.The discharge to VCP had a greater impact on the digital information compared to the discharge to HCP. To investigate this, experiments were conducted, varying the values of uncoupling capacitances in the digital shift circuit. It was observed that circuits with smaller uncoupling capacitances were more susceptible to ESD. On the other hand, circuits with higher uncoupling capacitances, such as 0.47µF, provided better protection against ESD due to their ability to reject high frequency ESD transients. Experimental studies on TTL and CMOS

logic Gates showed that CMOS devices were more prone to ESD compared to TTL devices. This was attributed to the presence of an insulator media in CMOS devices that easily broke down at high voltages. After ESD stress, the output of CMOS logic Gates deteriorated and did not recover after reset. Proper grounding was found to significantly reduce ESD susceptibility in the various mode circuit used. In this circuit, data was primarily affected by transients of different voltages when parallel and digital signals were common.This affirms that when both digital and parallel signals are present, the high frequency signals generated by the digital circuit (using a 555 Timer astable multivibrator circuit) can affect the output of the parallel circuit (using an inverting amplifier with opamp). However, when the digital and parallel signals are separated in different circuits, there are no transients caused by electrostatic discharge (ESD) in the parallel output. Therefore, it is recommended to keep the digital and parallel signals separate.

In an experiment with an 8-bit microcontroller diagnostic circuit, a direct discharge of 12 kilovolts was applied twice to the GPIO pin. This caused the resistance of the board to decrease significantly, indicating a short circuit between the VDD and VSS tracks of the microcontroller. As a result, the microcontroller shut down by activating its thermal shutdown feature. All three designed diagnostic tests for the digital ports, UART, and PWM channels failed. It was observed that the failure in the microcontroller occurred when the ESD event was closer to the Vcc and Ground pins, possibly because of capacitance across these pins due to the ESD event. Malfunctioning was predominantly observed for ESD events

at other pins.

On the other hand, the MSP430 launchpad with a 16-bit microcontroller is more resistant to ESD due to its built-in design and consideration for ESD protection.The effectiveness of protecting the communication port of the 16 spot microcontroller MSP 430G2231 IC from electrostatic discharge (ESD) was confirmed through experimentation using both direct and indirect ESD trials. However, when subjected to an 8kV direct contact discharge on the Tx-Rx pins of the jumper array, the communication port of the MSP 430G2231 IC was damaged, rendering it non-functional for the intended software program. To prevent such damage in the future, TVS rectifying tubes should be implemented to provide protection for the communication port. Unlike the 8 spot microcontroller system, which lacked additional on-board protection devices and did not withstand the recommended 15kV air discharge as per IEC standards, the MSP 430 launch tablet with the 16 spot microcontroller on a four bed PCB was designed with ESD considerations in mind. However, due to a lack of additional protection, the 16 spot microcontroller also did not withstand the recommended up to 8kV contact discharge at the communication port. It is important to note that continuous discharges on the 8 spot microcontroller resulted in thermal shutdown, while the continuous discharges on the 16 spot and 32 spot microcontrollers did not cause thermal shutdown, possibly due to their design on four bed boards.The usage designed four bed board with a 32 spot microcontroller is equipped with various components such as the UART, audio interface, USB, LCD display, and cardinal matrix. The board follows all standard design regulations for PCB design and includes two versions - one with on-chip

protection and another with off-chip on-board protection devices.

During the testing of the 32 spot microcontroller system on the four bed board, it was found that the arrangement of components on the board and the board design significantly contributed to the system's ability to withstand ESD. Adherence to standard design regulations, such as using split land and power planes, arranging components to minimize loop area, employing ferrite beads and uncoupling capacitors for power supply uncoupling, placing connections, user interfaces, and output devices at the edges of the board, and separating parallel and digital sections, all contributed to the boards' resilience against ESD. Additionally, strategically placed on-board protection devices at input/output points, data and power points, communication ports, and interface input points further enhance the system's robustness.The microcontroller board with on-chip protection is resistant to electrostatic discharge (ESD) due to its adherence to standard design regulations. However, it may still experience issues such as malfunction or reset on power activation, particularly affecting the LCD interface. On the other hand, the other board incorporates additional on-board protection features. These include a ferrite bead for isolating the noisy digital section from the parallel section, decoupling capacitances for power supply stability, a schottky rectifying tube for ESD protection of USB, and TVS rectifying tubes at various input points. This board experiences only temporary resets and is minimally affected by ESD. Furthermore, its interface functions normally. Based on experimentation, it has been determined that while the microcontroller board with on-chip protection mitigates damages, malfunctions still occur and require a hard reset to recover. Conversely, the inclusion of excess on-board protection eliminates damages, reduces malfunctions, and leads to only temporary resets.It

is necessary to not only implement standard board design regulations, but also provide on-board protection against electrostatic discharge (ESD) by using appropriate protection devices and placing them at strategic locations such as the input pins and supply pins of the device.

Experiments were conducted on the dielectrics in FPGA/CPLD kit, including a seven section LED display, LCD, and FRC, to test the effects of direct air discharge. Metal points such as switches, pins, and climb prison guard were also subjected to reach discharge.

An air discharge of 8 kilovolts on the Liquid Crystal Display caused data distortion, but resetting with power ON resolved the issue. However, an air discharge of 15kV caused irreparable damage to the LCD data upon reset.

Air discharges of 2kV and 4kV had no effect, while discharges of 8 kilovolts and 15 kilovolts caused output distortion on the seven section LED display, but reset back to normal when power was turned on.

Contact discharges of 2 kilovolts and 4kV on the HEX keys had no impact on the data feeding the seven section display. However, a contact discharge of 8 kilovolts caused a short circuit in the keys, resulting in incorrect display data.

All of these devices only had on-chip protection provided by the manufacturer, indicating the need for off-chip, on-board protection devices to reduce susceptibility to ESD.

Significant transients were observed when air discharge was conducted on the FRC cables connected to the DAC module.The reduction in DAC output voltage is observed when a 2 kilovolt contact discharge is applied to input pin 187 of the female parent baseboard. The contact discharge affects the FPGA 3s50 IC. Both direct and

indirect ESD effects cause damage to the DAC ICs. The CPLD 9572 IC is also affected by ESD. The ESD discharge on the FPGA/CPLD kit's input pin and its surroundings results in shorting and damage to the ceramic capacitance in the connected SMPS power supply. This damage is observed after the ESD trial, and it contributes to harm to the FPGA and CPLD ICs. Decapping of these ICs confirms their failure due to ESD, with damage to the input/output pin bond tablet and metatop bed of the FPGA 3s50 IC, as well as dielectric dislocation in the CPLD 9572 IC. These devices are highly susceptible to ESD. In terms of future scope, while there has been significant effort in understanding the impact of ESD on individual ICs and various circuits/systems, such as FPGA/CPLD kits and microcontroller units with different interfaces, less time has been devoted to modeling these circuits/systems and using simulation tools to analyze their behavior towards ESD.An attempt has been made to mathematically simulate the susceptibility of electronic systems and overseas telegrams to radiated ESD fields. In addition, circuit simulation has been conducted for parallel circuits. The experimental susceptibility trials on various electronic components have yielded both familiar and novel results, leading to new ideas for implementing ESD-protected circuitry/systems. The level of ESD threat to electronic components depends on the discharge voltage of the ESD source, the discharge point, and the construction and design of the component. The ESD threat to components mounted in systems may differ significantly from that of unmounted individual components. New models need to be developed to predict the behavior of devices while they are operating within a system,

and using computer simulations, it is essential to forecast the ESD voltage, power, and energy threats to system-mounted components. This is an area where the experimental results can be compared with simulated results to confirm the origin of the threat, the discharge point, and its impact on the system.New protection strategies can be adapted to make the system less susceptible to electrostatic discharge (ESD). Another country where ESD trials can be conducted is in the field of high velocity wireless radio frequency (RF) circuits and systems. As the demand for RF and high-velocity mixed-signal systems continues to increase rapidly, providing sufficient ESD protection for these systems is a major design and reliability challenge. This is because the protection system must be transparent - it should not affect the signal under normal operating conditions. A poorly designed protection system can result in resistance mismatches, signal reflections, signal integrity degradation, and inefficient power transfer between the signal pin and the core circuit. ESD parasitic capacitance poses an even greater challenge for broadband RF system protection, which may require alternative protection strategies. Therefore, it is important to first understand the effects of ESD on these high velocity RF systems. However, there is limited published information available that provides performance analysis of RF circuits with various ESD protection design options, especially for operations in the multi-GHz range.