Buck Converter Design Demystified Essay Example

is usually the case. CM implies that the inductor does not fully discharge during the switch-off time. The following equations assume an ideal switch (zero on-resistance, infinite off-resistance and zero switching time) and an Ideal diode: where FSP is the buck-converter switching frequency and LIRA Is the inductor-current ratio expressed as a percentage of TOUT (e. . , for a 300-map-p ripple current with a I-A output, LIRA = 0. 3 All A 0. 3 LIRA). An LIRA of 0. 3 represents a good tradeoff between efficiency and load-transient response. Increasing the LIRA constant -? allowing more inductor ripple current -? quickens the load- rainiest response, and decreasing the LIRA constant-? thereby reducing the inductor and inductor current for a given load current, for LIRA constants ranging from 0. 2 to 0. 5. Peak current through the inductor determines the inductor's required saturation-current rating, which in turn dictates the approximate size of the inductor.

Saturating the inductor core decreases the converter efficiency, while increasing the temperatures of the inductor, the MOSSES and the diode. You can calculate the inductor's peak operating current as follows: For the values listed in Fig. 1, these equations yield a calculated inductance of 2. 1 pH (LIRA = 0. 3). Select an available value that is close to the calculated value, such as a 2. 8 pH, and make sure that its saturation-current rating is higher than the calculated peak current (PEAK = 8. 9 A). Choose a saturation-current rating that's large enough (10 A in this case) to compensate for circuit tolerances and the difference between actual and calculated component values. An acceptable margin for this purpose, while limiting

the inductor's physical size, is 20% above the calculated rating. Inductors of this size and current rating typically have a maximum dc resistance range (DC) of 5 m! O 8 m!. To minimize power loss, choose an inductor with the lowest possible DC.

Although data sheet specifications vary among vendors, always use the maximum DC specification for design purposes rather than the typical value, because the maximum is a guaranteed worst-case component specification. Output Capacitor Selection Output capacitance is required to minimize the voltage overshoot and ripple present at the output of a stepsons converter. Large overshoots are caused by insufficient output capacitance, and large voltage ripple is caused by insufficient capacitance as ell as a high equivalent-series resistance (USER) in the output capacitor.

The maximum allowed output-voltage overshoot and ripple are usually specified at the time of design. Thus, to meet the ripple specification for a stepsons converter circuit, you must include an output capacitor with ample capacitance and low USER. The problem of overshoot, in which the output-voltage overshoots its regulated value when a full load is suddenly removed from the output, requires that the output capacitor be large enough to prevent stored inductor energy from launching the output above the specified maximum output voltage. Output-voltage overshoot can be calculated using the following equation: Rearranging CEQ. Yields: where CO equals output capacitance and "V equals maximum output-voltage overshoot. Setting the maximum output-voltage overshoot to 100 NV and solving CEQ. 3 yields a calculated output capacitance of 442 IF. Adding the typical capacitor-value tolerance (20%) gives a practical value for output capacitance of approximately 530 IF. The closest standard value is 560 IF. Output

ripple due to the capacitance alone is given by: USER of the output capacitor dominates the output-voltage ripple. The amount can be calculated as allows: Be aware that choosing a capacitor with very low USER may cause the power converter to be unstable.

The factors that affect stability vary from ICC to 'C, so when choosing an output capacitor, be sure to read the data sheet and pay special attention to sections dealing with converter stability. Adding the output-voltage (the second term in CEQ. 4) yields the total output-voltage ripple for the stepsons converter: A decent stepsons converter usually achieves an output-voltage ripple of less than 2% (40 NV in our case). For a 560-if output capacitance, CEQ. 5 yields 18. 8 m! For the maximum calculated USER. Therefore, choose a capacitor with USER that's lower than 18. M! And a capacitance that's equal to or greater than 560 IF. To achieve an equivalent USER value less than 18. 8 m! , you can connect multiple low-USER capacitors in parallel. Fig. 3 presents output-ripple voltage versus output capacitance and USER. Because our example uses tantalum capacitors, capacitor USER dominates the output- voltage ripple. Input Capacitor Selection The input capacitor's ripple-current rating dictates its value and physical size, and the following equation calculates the amount of ripple current the input capacitor must be able to handle: Fig. Lots ripple current for the capacitor (shown as a multiple of the output current) against the input voltage of the buck converter (shown as a ratio of output voltage to input voltage). The worst case occurs when VINE ABOUT (VOTING = 0. 5), yielding AUTOMAT / 2 for the

worst-case replacement rating. The input capacitance required for a stepsons converter depends on the impedance of the input power source. For common laboratory power supplies, 10 if to 22 if of capacitance per ampere of output current is usually sufficient. Given the design parameters of Fig. 1, you can calculate the input-ripple current as 3. A. You then can start with 40 if in total input capacitance and can adjust that value according to subsequent test results. Tantalum capacitors are a poor choice for input capacitors. They usually fail "short," meaning the failed capacitor creates a short circuit across its terminals and thereby raises the possibility of a fire hazard. Ceramic or aluminum-electrolytic capacitors are preferred because they don't have this failure mode. Ceramic capacitors are the better choice when PC-board area or component height is limited, but ceramics may cause your circuit to produce an audible buzz.

This high-pitched Jose is caused by physical vibration of the ceramic capacitor against the PC board as a result of the capacitor's ferroelectric properties and piece phenomena reacting to the voltage ripple. Polymer capacitors can alleviate this problem. Polymer capacitors also fail short, but they are much more robust than tantalums, and therefore are suitable as input capacitors. Diode Selection Power dissipation is the limiting factor when choosing a diode. The worst-case average power can be calculated as follows: where VT is the voltage drop across the diode at the given output current AUTOMAT. Typical values are 0. V for a silicon diode and 0. 3 V for a Scotty diode. ) Ensure that the selected diode will be able to dissipate that much power. For reliable

operation over the input-voltage range, you maximum input voltage (VRRP VIVIAN). The diode's forward-current specification must meet or exceed the maximum output current (I. E. , AVIVA AUTOMAT). MOSSES selection Selecting a MOSSES can be daunting, so engineers often avoid that task by choosing a regulator ICC with an internal MOSSES.

Unfortunately, most manufacturers find it cost prohibitive to integrate a large MOSSES with a dc-dc controller in the same package, o power converters with integrated Moslems typically specify maximum output currents no greater than 3 A to 6 A. For larger output currents, the only alternative is usually an external MOSSES. The maximum Junction temperature (TAX) and maximum ambient temperature (TAMA) for the external MOSSES must be known before you can select a suitable device. TAX should not exceed 1 1 ICC to CHIC and TAMA should not exceed CHIC.

A CHIC maximum ambient temperature may seem high, but stepsons converter circuits are typically housed in a chassis where such ambient temperatures are not unusual. You can calculate a maximum allowable enrapture rise for the MOSSES as follows: Inserting the values mentioned above for TAX and TAMA into CEQ. 7 yields a maximum MOSSES temperature rise of CHIC. The maximum power dissipated in the MOSSES can be calculated from the allowable maximum rise in MOSSES temperature: The type of MOSSES package and the amount of PC-board copper connected to it affect the Onset's Junction-to-ambient thermal resistance ($JAG).

When $JAG is not specified in the data sheet, cancan' serves as a good estimate for a standard SO-8 package (wire-bond interconnect, without an exposed paddle), mounted on 1 in. 2 of I-oz PC-board copper. There exists

no inverse linear relationship between a $JAG value and the amount of copper connected to the device, and the benefit of decreasing the $JAG value quickly dwindles for circuits that include more than 1 sq in. Of PC-board copper. Using $JAG = cancan' in CEQ. 8 yields a maximum allowable dissipated power in the MOSSES of approximately 0. 9 W. Power dissipation in the MOSSES is caused by on-resistance and switching losses. On- resistance loss can be calculated as: Because most data sheets specify the maximum on-resistance only at CHIC, you may have to estimate the value of on-resistance at TOOK. As a rule of thumb, a temperature coefficient of 0. 5%/C provides a good indicator for maximum on-resistance at any given temperature. Thus, the hot nonresistance is calculated as: Assuming the on-resistance loss is approximately 60% of the total MOSSES losses, you can substitute in CEQ. 0 and rearrange to yield CEQ. 11, the maximum allowable on-resistance at CHIC: Switching losses constitute a smaller portion of the Onset's power dissipation, but they still must be taken into account. The following switching-loss calculation provides only a rough estimate, and Hereford is no substitute for evaluation in the lab, preferably a test that includes a thermocouple mounted on Pl as a sanity check. Where CROSS is the reverse-transfer capacitance of Pl, IGATE is the peak gate-drive source/sink current of the controller and Pl is the high-side MOSSES.

Assuming a gate drive of 1 A (obtained from the gate driver/ controller data sheet) and a reverberates capacitance of 300 if (obtained approximately 26. 2 m!. Recalculating and summing the on-resistance losses and the switching losses yields a

net dissipated power of 0. 676 W. Using this figure, you can lactate for the MOSSES a maximum temperature rise of 101 co, which is within the acceptable temperature range. Stepsons-converter Efficiency Minimizing power loss throughout the converter will extend battery life and reduce heat dissipation.

The following equations calculate power loss in each section of the converter. Input capacitor USER loss: PICRIC =localism x CERCI. Refer to Sees. 6, 9 and 12 for losses due to the diode, the MOSSES on-resistance and the MOSSES switching loss. Inductor DC loss: Pc-board copper Loss: Pc-board copper loss is difficult to calculate accurately, but Fig. Provides a rough estimate of the amount of resistance per square area of PC-board copper. With Fig. 5, you can use a simple ERR power dissipation equation to calculate the power loss.

The following equation sums all of the power losses throughout the converter, and accounts for those losses in the expression for converter efficiency: Assuming a reasonable net copper loss of approximately 0. 75 W, the efficiency for this converter is 69. 5%. Replacing the silicon diode with a Scotty diode increases the efficiency to 79. 6%, and replacing the diode with a MOSSES synchronous rectifier further increases the efficiency to 85% at full dad. Fig. 6 depicts a breakdown of power losses in the converter.

Doubling the copper weight to 2 oz or tripling it to 3 oz minimizes the copper loss and thereby increases the efficiency to approximately 86% to 87%. Careful PC-board layout is critical in achieving low switching losses and stable operation for a stepsons converter. Use the following guidelines as a starting point: Keep the high-current

paths short, especially at the ground terminals. Minimize connection lengths to the inductor, MOSSES and diode/synchronous MOSSES. Keep power traces and load connections short and wide. This practice is essential for high efficiency.

Keep voltage- and current-sensing nodes and traces away from switching nodes. Verifying Performance When designing or modifying a stepsons switching-regulator circuit (one that operates in CM, using PAM), you can use the equations in this article to calculate values for the critical components and characteristics required. You should always lab-test the circuit to verify final electrical and thermal specifications. For acceptable circuit operation, a proper PC-board layout and Judicious component placements are as critical as choosing the right components.