Constant Frequency Unified Power Quality Conditioner Engineering Essay Example

the shunt inverter's end product current and are fed to a hysteresis type (PWM) current accountant. However, there are some issues with UPQC. This modified incorporate power quality conditioner construct enables the PWM converter to perform not only active filtrating intent but also the function of a frequency modifier.

The upcoming subdivisions will cover the compensation rule of the CFUPQC. The proposed power quality conditioner must meet the following requirements: maintaining reactive power at a minimal value, keeping the burden voltage at the rated supply voltage, maintaining input current with very low harmonic content, and ensuring the supply frequency is within acceptable power quality limits. The simulations' results will validate the proposed CFUPQC.

In order to determine the frequency of the power system during normal operation, certain indices are used. This includes the relative frequency deviation and the inherent deviation during the required hold to ensure proper synchronization of clocks with the electrical network frequency. According to the En 50160/2006 standard, the rated frequency of the supply voltage is 50Hz. Under normal operation, the average value of the central frequency measured over time should fall within certain ranges. For 99.5% of the year, it should be 49.5-50.5Hz (50Hz + 1%). For 100% of the time, it should be 47-52Hz (50Hz + 4%). However, since the power frequency may not be exactly 50Hz at all times, the central frequency output is calculated by counting the number of integer cycles within a 10s time interval divided by the cumulative value of the integer cycles. The measures taken to maintain the frequency within required limits are aimed at minimizing deviations from the normalized value.

In this way, an analysis of the

effect of frequency fluctuation on the final client is only for a reduced interval of about +3Hz of the rated value and for a short period. Within the reduced fluctuation range (40%), a significant number of passive clients are not affected by the system fluctuation (rectifier, opposition, ovens, electric discharge ECT), but 60% of the consumers (fans, motors ect) are affected by the frequency fluctuations. The asynchronous and synchronous driving motors connected to the supply web used extensively in single acceleration have power frequency alterations. Depending on the mechanical characteristic velocity of the motor and also depends on the supply frequency [13]. The speed of asynchronous motors or synchronous motor unlimited retarding forces to the electric power supply fluctuations s relative to the applied electromotive force frequency. The frequency fluctuation leads to the corresponding alteration of the process production time throughout the supply, with a decreased frequency dejecting the supply frequency capacitive circuit, transformer, relay spiral are affected Modified configuration of UPQC consists of shunt active filter, series active filter, voltage source inverter, and voltage source converter shown in .CFUPQC similar to the UPQC except for the frequency altering section.

The intercrossed filtering public presentation of UPQC may have possible drawbacks, as its filter features rely on load electric resistance and supply frequency. However, CFUPQC series active filter can compensate for electromotive force harmonics and electromotive force instability. Additionally, the electromotive force beginning convertor supplies AC to DC power, which is fed to a common DC nexus. The CFUPQC includes a parallel active filter (PAF) that eliminates load harmonics and compensates for load reactive power. Its control equation is Ipf=G.IL, where g is the control map

and IL is the burden current. The input current constituents for compensation are extracted from the burden current and burden electromotive forces using theory. The convertor is a current controlled device with a 20 kilohertz clocked hysteresis set. There is also a series active filter (SAF) that compensates for supply harmonics spark, electromotive force sag/swell, imbalance, and rectifying tube + capacitance type burden harmonics to flux into the parallel filter.

The control equation involves the variables K, Usf, Ish, and Ucomp. K represents the addition of the regulator, Usf is the electromotive force of the series filter, Ish refers to the harmonic supply current, and Ucomp represents the compensation electromotive force necessary to account for imperfections in the supply electromotive force. The extraction of Ish is based on theory.

To facilitate the transmission of real power to/from a common DC bus and to control the DC bus, an Active Rectifier (AR) is used. The use of a series inverter can reduce the average value of the DC bus by minimizing switching losses and power received from the DC link capacitors.

Imbalanced conditions and sudden alterations in burden current can cause oscillation in the District of Columbia coach electromotive force. To resolve this issue, a three stage rectifier is employed. The fluctuated District of Columbia electromotive force is regulated by a three-phase rectifier convertor to enable bi-directional power flow, and its control ensures insensitivity to supply voltage imperfections. The Rms value of the output electromotive force (Vorms) is equal to 0.9558 times the maximal value of line current (Vml), while the Rms value of the output current (Iorms) is equal to 0.9558 times the maximal value of line current

(Iml). In order to maintain a constant DC coach electromotive force, a multi-phase 48 pulse electromotive force source inverter (VSI) is employed to supply a constant power frequency even when the supply frequency varies. Furthermore, a multilevel electromotive force source inverter is used to eliminate the harmonic component of the output.

The frequency converter is positioned between the series and shunt active filters. Typically, the rectifiers in the power supply generate current harmonics. To prevent these harmonics and reactive power, the rectifier is placed between the two active filters. Additionally, if the load increases, there may be a voltage dip in the input of the voltage source inverter. However, at the same time, the series active filter compensates for these voltage issues.

The shunt inverter commanding block diagram of CFUPQC is shown in the figure. It utilizes synchronal mention frame theory to measure the sensitive tonss current. The mensural currents of the burden are converted into border utilizing sinusoidal maps through synchronal mention frame transition. The sinusoidal maps are obtained through the grid electromotive force using the phase lock loop (PLL). The currents are divided into ac and dc components, denoted by equations and . These components can be derived by low pass filter. and represent the DC and AC constituents, respectively. The control algorithm corrects the systems power factor and compensates all the current harmonics by generating the reference currents given in equation . The reference current is transferred into border through reverse transition of synchronal mention frame.

The output of the shunt inverter is sent to the hysteresis set accountant. This generates the necessary control pulses and compensation current for the inverter's power switch gates.

The 48-pulse electromotive force beginning converter includes four 3-phase, multi-level inverters and four phase-shifting transformers with a stage displacement of +/- 7.5; grade. This transformer arrangement eliminates all odd harmonics up to the forty-fifth harmonic.

Using eight 6-pulse inverters, a 48-pulse waveform is achieved to reduce harmonic content. This is accomplished by applying stage displacements to the inverter voltages in two steps: firing pulses and Zig-zag transformers. The resulting waveform eliminates all odd harmonics up to the forty-fifth harmonic, except for the 23rd and 25th harmonics. The natural harmonics of the Y and D transformer secondary include 5+12n (5, 17, 29, 41, ...).

) and 7+12n (7, 19, 31, 43, ...). In addition, the 15° phase switch between the two groups of transformers (Tr1Y and Tr1D lagging by 7.5°, Tr2Y and Tr2D lagging by 7.5°) enables the cancellation of harmonics 11+24n (11, 35, ...) and 13+24n (13, 37, ...).

) . The transformers do not transmit all 3n harmonics. Therefore, the first harmonics that are not cancelled out by the transformers are the 23rd, 25th, 47th, and 49th harmonics. By using the appropriate conductivity angle ( ? = 172.5 ; A ; deg ; ) for the three-level inverter, the presence of the 23rd and 25th harmonics can be reduced. As a result, the main harmonics generated by the inverter will be the 47th and 49th harmonics.

Using a bipolar DC electromotive force, the electromotive force beginning inverter generates a 48-step electromotive force to achieve a sine wave. The secondary sides of the yoke transformers are connected in series to add up the output electromotive forces of individual VSIs, resulting in a multi-pulse stage electromotive force expressed mathematically

as equations  and  . These equations represent phase-to-phase and phase-to-neutral electromotive force representations respectively, demonstrating inherent filtering of harmonics up to the 47th order. The signalisation of the 48-pulse inverter is generated with a -41.25 gate pulse stage and fed directly to the corresponding inverter. PWM signals for the remaining inverters are obtained by applying relevant stage displacements to the set of PWM signals generated. For example, to obtain the pulsations for the inverter with a -11.25o gate pulse, a +30o stage displacement is applied to the output of the closed loop current regulator.

The stage shifting of the pulsations in pattern is achieved by using a hold in the first rhythm. The earliest set of pulsations is generated, followed by delayed generation of the remaining sets, since a negative hold cannot be used. If the supply frequency exceeds the power quality limit, the constant frequency voltage source inverter control system switches the load from the source power supply to the constant frequency inverter power supply. However, when the supply frequency exceeds the power quality limits, the operation of UPQC does not produce satisfactory results. At 0.25 second, when the supply exceeds the power quality limit (greater than 63 Hz), the waveform of the load voltage varies. As the frequency increases, the waveform of the voltage becomes highly distorted, as shown in the simulation results. Based on Figure 10 of the simulation results, it can be inferred that if the supply frequency exceeds the power quality limit, the waveform of the load current will become distorted.

If the frequency increases, the waveform also quickly distorts, as shown in fig10. The simulation above demonstrates that the 48-pulse inverter

handles the load current when the supply frequency varies beyond the power quality limit. When the frequency surpasses the limit at 0.28 sec, the voltage source converter supplies the power. This paper introduces a integrated system of UPQC and variable frequency converter, along with the control system for each VSC. With this proposed system, the CFUPQC performs well when the supply frequency exceeds the power quality limits.

As a result, we can provide a continuous power frequency to the load side without making any changes to the control system. MATLAB software simulations demonstrated the advantageous features of this proposed system.