Thyristor Ram Essay Example

use of a thyristor structure, called thin capacitively coupled thyristor TCCT.

3: Working:

The fundamental component of a thyristor based cell structure is the internal thyristor latch. A CMOS-based thyristor device known as a Thin Capacitively Coupled Thyristor has been introduced as a novel switching device for high-density high-performance memory applications in thyristor based memory cells.

The switching speed of the TCCT device is determined by various device parameters such as npn and pnp bipolar gains, gate to-p base capacitive coupling ratio, and carrier lifetime in J1. Due to the unique gate coupling mechanism, the excess carriers in the p-base are removed at the falling edge of the gate pulse without carrier recombination; however, carriers in the n-base need to be removed by recombination. Therefore, the carrier lifetime in the J1 junction becomes a limiting factor for the turn-off switching speed. When  is reduced, carriers in the n-base are more quickly recombined, resulting in improved turn-off speed.

The switching speed of the TCCT device is determined by various device parameters such as npn and pnp bipolar gains, gate to-p base capacitive coupling ratio, and carrier lifetime ? in J1. Due to the unique gate coupling mechanism, the excess carriers in the p-base are removed at the falling edge of the gate pulse without carrier recombination; however, carriers in the n-base need to be removed by recombination. Therefore, the carrier lifetime in the J1 junction becomes a limiting factor for the turn-off switching speed. When  is reduced, carriers in the n-base are more quickly recombined, resulting in improved turn-off speed.

The gain of bipolar transistors increases with temperature. Indium is employed as the p-base dopant species in order to modulate the

temperature coefficient of NPN gain and stabilize thyristor characteristics over a wide operating temperature range. The base of an NPN bipolar transistor is typically doped with boron, which is nearly fully ionized over the operating temperature range of most semiconductor devices. Indium is known to have an acceptor level which is 156 meV above the top of the valence band of silicon. As a result, the fraction of ionized indium atoms increases with temperature, esulting in reduced gain. Such a thyristor that has good thermal stability, large switching speed and a small fabrication size is used to create memory cells.

Two possible thyristor cell structures for memory devices are as follows:

At this moment, the thyristor behaves like a reverse biased diode. After the write operation, both gates are shut off, and a "low" state is stored in the thyristor Read operation: In a read operation, only the first word-line WL1 is activated. The bit-line current is sensed by a sense amplifier. A large current will indicate logic ‘1’ and vice versa. During the stand-by ‘ON’ state the holding current to the thyristor is provided by the sub-threshold current of the access transistor Simplified diagram and waveforms:

Thyristor based D-RAM:

CONCEPT:

The new TCCT DRAM memory cell is constructed using three control lines; bit line, word line, and write enable line. The anode node is connected to a bit line and the cathode node is connected to a word line. The gate poly line itself functions as a write enable line. For write 1, gate line is pulsed while cathode line is held at ground level, triggering the TCCT device to latch. The bias scheme for write zero operation

is the same as write one except that bit line voltage is kept low so that the pulsing of the gate line switches the TCCT into its blocking state.

For Read operation, the cathode line is held low and the change in the voltage or the current of the bit-line is read into a sense amplifier. The write enable line at the gate is not active in read operation. In standby mode, both anode and cathode lines are at Vdd and the stored cell data is maintained by the charge state of the P-base of TCCT. Waveforms:

The Thyristor-RAM macro provides the highest combination of performance and density among all embedded memories solutions. A Thyristor-RAM macro matches 6T-SRAM in performance while providing 2-3x higher macro density, and lower power consumption. The Thyristor-RAM is fully CMOS compatible and can be readily integrated with a baseline CMOS technology on either Bulk or SOI substrates without any impact on the baseline technology transistors. Thyristor –RAMs have been fabricated and have proven their efficiency in 130 nm SOI mode. Thyristor DRAMS are now targeting 45 nm, 32 nm and 22 nm mode.

In future, Thyristor-rams can be used to reduce the chip size or to increase the capacity of cache memory in processors. Cell size comparison of t&s-ram There are some drawbacks that may limit the adoption of thyristor based memory storage cells as SRAM replacement in high speed memory applications. T-RAM states that the TCCT test chip was fabricated on the standard 130 nm high performance SOI process with 16 additional process steps added. However, most of the steps are simple implant-only steps, and the same mask set is used for

several of the additional processing steps.