Electronics Coursework Electronic Combination Lock Essay Example

the physical lock itself would employ a solenoid to activate its mechanism. Additionally, I have conducted research on mechanical locks. The following section will detail the components I will utilize in constructing my circuit and elucidate their functionality through various calculations.

To generate the necessary memory for remembering the required combination of switch presses, I will utilize 4013b CMOS chips, which are D-type flip-flops. In the following explanation, I will outline the functioning of CMOS 4013b and provide a pinout diagram for reference. Each flip-flop can be used separately.

There are two models, clocked and direct. In the clocked mode, the direct set and reset inputs must stay at ground. The input to the D line determines the flip-flop's action. The action takes place at the positive edge (ground-to-positive transition) of the clock. If D is positive, clocking causes the Q output to be positive and Q dash to be grounded. If D is grounded, clocking causes the Q output to be grounded and Q dash to be positive.

In direct mode, if the positive set input is active, both Q and Q' will be grounded. If the positive reset input is active, Q will be grounded and Q' will be positive. If both reset inputs are activated simultaneously, both Q and Q' will become positive, which is generally not allowed. The final state of the Q and Q' outputs will be determined by which direct input is grounded last.

Priority is given to direct inputs over clocked inputs. Each flip-flop for binary division can be connected in such a way that the D input receives the negated Q output. The clock input should be clean of noise and

have only one rising edge per cycle. The rise and fall times of the clock must not exceed 5 microseconds. At 10 volts, the maximum clock frequency is 10 megahertz; at 5 volts, it is 4 megahertz. At a clock frequency of 1 megahertz, the total package current is 0.8 milliamperes at 5 volts and 1.6 milliamperes at 10 volts.

Reference: taken from "CMOS Cookbook" * In my circuit, I plan to use momentary switches or push button switches. A push-button switch is known as a "momentary" switch because it doesn't remain in position after you remove your finger. For example, a doorbell button is a "normally open" (N.O.) momentary switch. When you press it, the circuit is connected and the bell rings. When you release it, the circuit is disconnected and the bell stops ringing. A crucial aspect of my project is ensuring that all the switches cannot be pressed simultaneously to activate the unlocking sequence.

In order to enhance the security of the lock, I will implement a system where the switches must be pressed in a specific sequence. To achieve this, I will utilize a series of latches as a form of memory, ensuring that the lock cannot be opened without knowing the correct code. This method will greatly improve the lock's security. In terms of circuitry, I have identified a compatible circuit diagram for the combination lock I intend to construct. Additionally, I will be using a BFY51 transistor to amplify the signal before it activates the relay. Below, you can find the pinout and an explanation of the functional properties of the BFY51.

It includes the three active components necessary while still

maintaining simplicity to realistically complete the construction, fault find, and test the circuit within the assigned time limit. The circuit needed to be connected to a relay to power a solenoid for opening the lock mechanism, as the voltage used by the switch entry circuitry was only 5 volts on average, much lower than the mains voltage used by the solenoid circuit. I had an alternative circuit solution that was significantly more complex and contained more active components, but I decided to use the less complicated circuit to ensure timely project completion. Sub-System Development: * I have the flexibility to determine the sequence of switches that need to be pressed in order to open the lock. The switches not in use are connected in parallel, so pressing any of them will reset the circuit.

The switches used are connected to the 4013b CMOS chips. Pressing a switch sends a signal to the next chip, indicating that it has been pressed correctly and enabling the activation of the next chip for the next switch to be activated. This means that the switches must be input in a specific correct sequence. If the combination is entered incorrectly, the circuit is reset and the combination must be input again. To create memory for remembering the required order of switch presses, I am using 4013b CMOS chips.

The combination lock's assembly diagram is displayed in the following :

. To unlock the lock, press the momentary switches (S1, S2, S3, S4) in the specified order. The lock is connected to the K1 Load.

If any of the other switches are pressed, the circuit will reset and you will need to begin again.

Depending on how you connect the switches, any combination of four switches can be used. However, I will not use the standard combination of 1->2->3->4. Changes to this code will be made accordingly.